Functional verification Interview Preparation course
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Functional verification interview preparation course
- Course Duration: 50 Hours
- 4.6 Star (Rating)
- 700+ (Student Enrolled till Now)
VLSI functional verification is a 50+ hours course covering all the aspects of Verilog, SV and UVM. It includes both theoretical and use case implementation
for all SV and UVM language constructs.
Course includes collection of important questions in all SV & UVM topics, mostly questions asked in product company interviews. Course is meant for those trying for product company placements.
Course highlights
- Covering 1200+ questions on Verilog, SV, UVM
- Mostly coding based questions
- Questions based on TB component development
- Questions based on features listing down, test plan development, testbench architecture
- Questions based on test case coding, sequence coding
- Coding by referring to timing diagram
- Debugging based questions
- Design bug reporting and how to fix based questions
- Analyze the given code, how to find errors in the code
- Timing diagram drawing questions
| Unit Number | Topic | Duration (Mins) |
| 1 | Training overview | 16 |
| 2 | Constraint theory Part1 | 65 |
| 3 | Constraints theory Part2 | 32 |
| 4 | Array randomization with some conditions | 7 |
| 5 | Number pattern generation | 16 |
| 6 | Real random number generation | 6 |
| 7 | randc using rand | 7 |
| 8 | number pattern generation | 18 |
| 9 | Array 3 elements same rest unique | 10 |
| 10 | Prime number generation | 42 |
| 11 | 2 Dimensional array constraint | 11 |
| 12 | Write Read Tx constraint | 15 |
| 13 | Dynamic array constraint | 7 |
| 14 | Slave select constraints example | 11 |
| 15 | USB packet generation | 52 |
| 16 | Descriptor array randomization | 30 |
| 17 | 2D bit array randomization | 22 |
| 18 | Multiple queues unique element randomization | 15 |
| 19 | Array randomization with minimum occurrence | 23 |
| 20 | Picking colored balls in a pattern | 35 |
| 21 | Array randomization with unique values | 5 |
| 22 | Dynamic array with minimum occurrence | 18 |
| 23 | sudoku puzzle Part1 | 4 |
| 24 | sudoku puzzle Part2 | 24 |
| 25 | Data pattern generation | 23 |
| 26 | 2D array randomization with max unique | 14 |
| 27 | array odd even element sum constraint | 6 |
| 28 | Object oriented programming | 175 |
| 29 | Object oriented programming | 106 |
| 30 | OOP - Class methods, Parameterized class | 186 |
| 31 | OOP - Inheritance, Polymorphism | 70 |
| 32 | OOP - $cast, Scope resolution operator, nested class | 41 |
| 33 | Functional coverage and code coverage basics | 77 |
| 34 | Functional coverage - cross coverage, intersect, bin types | 92 |
| 35 | transition coverage, code coverage, analysing coverage report, Constraint questions, Assertions | 105 |
| 36 | Assertions - practical examples | 84 |
| 37 | Assertions - Listing down assertions | 63 |
| 38 | Writing assertion for req resp protocol with corner cases | 8 |
| 39 | Previous session doubts, Arrays, mailbox | 77 |
| 40 | Operators, fork-join, interface, clocking block, common array methods, callbacks | 97 |
| 41 | System Verilog all topics revision | 134 |
| 42 | Scheduling semantics, `uvm_do_pri, sequence priority, writing a checker | 94 |
| 43 | UVM basic questions | 49 |
| 44 | Root, UVM TB basics | 35 |
| 45 | UVM Objections | 35 |
| 46 | UVM command line processor | 11 |
| 47 | UVM common phases | 13 |
| 48 | Reporting classes | 22 |
| 49 | Factory | 22 |
| 50 | UVM Config db and resource db | 30 |
| 51 | TLM | 46 |
| 52 | Driver-Sequencer communication | 7 |
| 53 | Test library, Sequence library | 24 |
| 54 | Sequence and Sequencer relation | 10 |
| 55 | Uvm_do macro variations | 1 |
| 56 | Factory registration, new, create, front door and back door access | 88 |
| 57 | UVC types, Common phases, TLM, virtual sequencer, sequence library | 88 |
| 58 | APB Monitor and Scoreboard coding | 25 |
| 59 | clocking block, modport, input and output skew, memory checking using front door and backdoor access, SOC and IP TB difference, SOC boot sequence | 81 |
| 60 | Sequence library, test library, mapping sequence to sequencer, uvm_do variations, sequence layering | 68 |
| 61 | UVM - Different styles of sequence coding(interrupt, power up, reset, DMA), Sequence layering, lock and grab methods, TLM2.0, uvm_barrier, Policy classes, | 84 |
| 62 | UVM advanced topics - event pool, phase jumping, register model, callbacks, UVM heartbeat | 80 |
| 63 | setup and hold time violation fixing, FSM development, Assertion coding, clock frequency division, SOC reset sequence | 138 |
| 64 | Scoreboard, singleton class, Router scoreboard implementation | 68 |
| 65 | UVM sequence, scoreboard, Async FIFO test plan questions | 33 |
- Sreenivasa Reddy
- Founder, VLSIGuru
Price - ₹8,000 + GST
₹10,000 (20% Off)
10 hours left to avail at this price
Course Highlights
- Mentor Support for doubt clarifications
- Product company focused questions
- 50+ hours of lectures
TESTIMONIALS
What Our Students Says About Inskill
Best Institute for VLSI DOMAIN. The Faculty is friendly.
In videos Srinivas Sir is the best in teaching.
The Lab Session are very very Good They will clear your all the doubts.
They Conduct PPT presentations Session for students for real experience and
Mock iAnd thanks to srinivas Reddy sir and monahar sir to solve my issuenterviews
And thanks to srinivas Reddy sir and monahar sir to solve my issue
Anytime I need help, Sreenivas sir(founder) was always there to help me. He cleared my doubts very well. This institute's placement support is excellent. So I am feeling very happy that I made the right decision to choose this institute for my training. Thank u so much Sreenivas sir.
It is actually a good institute for verification, those who are ready to work hard should definitely join, as the content quality is really worth, there projects are also good, after training you can compare with other institute candidates. Fees is very less compare to other institute as they don't provide system there, you have to take your own laptops, also there is advantage of video lectures, so whenever you got stuck u can refer it anytime, just you should be passionate and eager to learn more.. in respect of placement they provide you many service based companies, n few product based also if you are really good, then Srinivas sir will personally recommend your profile to companies, u just need to work hard, also in admin Prabhakar is there who will check if you are getting any difficulties.. overall I must recommend for this institute, and this is my honest review as I am trained from this institute
Excellent faculties with good course content . Happy with the support system provided though you can find sometimes issues with management. Nonetheless, placement support is incredible. Helped me to get placed in Capgemini.